1. Field of the Invention
The present invention generally relates to pseudo-differential switched-capacitor circuits, referred to as an integrator-based common-mode stabilization technique.
2. Description of the Prior Art
High-precision switched-capacitor circuits require high-gain and high-linearity amplifiers, which dominate the performance of the switched-capacitor circuits. The modern process tends toward low operating voltage to improve the circuit performance. This tendency leads to limited signal range and thus the design complexity. Further, the amplifiers may consume more power in order to maintain the signal-to-noise ratio.
Fully differential amplifier 10, as shown in FIG. 1A, is conventionally used to increase noise-immunity and signal swing. A common-mode feedback circuit (CMFB) 102 is required in the fully differential amplifier 10 to stabilize its output common-mode voltage (at the output node Out+/Out−). As the circuit's total current is controlled by a tail current metal-oxide-semiconductor (MOS) transistor Mc1, the common-mode disturbance at the input node In +/In− will not affect the circuit performance. The fully differential amplifier 10 therefore has high common-mode rejection ratio (CMRR). However, the transistor Mc1 disadvantageously limits the output signal range, and thus is unfavorable for low operating-voltage process. In order to enlarge the output signal range, a pseudo-differential amplifier 12, as shown in FIG. 1B, is conventionally used. The pseudo-differential amplifier 12 eliminates the tail current MOS transistor Mc1 of FIG. 1A, at the cost of losing common-mode noise-immunity. Accordingly, the input common-mode noise (at the input node In +/In−) will be amplified by the pseudo-differential amplifier 12, thereby degrading the circuit performance. The operations of the fully differential amplifier 10 and the pseudo-differential amplifier 12 are demonstrated in the following paragraphs in turn.
FIG. 2 schematically illustrates the operation of a switched-capacitor circuit 20 using the fully differential amplifier 104. In the illustration, only the common-mode voltage disturbance (ΔVcm) is considered while ignoring other alternating-current (AC) signals. In the sample phase, as shown in the left hand of the figure, the common-mode voltage disturbance (ΔVcm) is sampled by two capacitors C. In the amplify phase, as shown in the right hand of the figure, the output common-mode voltage can be maintained at Vcm due to the common-mode feedback circuit (CMFB). According to the conservation of charge, the common-mode voltage Vx at the input node of the amplifier 104 can be derived as shown in the figure. The input common-mode voltage disturbance (ΔVcm) will be reflected into the input common-mode voltage Vx. Nevertheless, the amplifier 104 can tolerate the common-mode voltage disturbance (ΔVcm) whenever the amplifier 104 has sufficient input common-mode range.
FIG. 3 schematically illustrates the operation of a switched-capacitor circuit 30 using the pseudo-differential amplifier 124. As the pseudo-differential amplifier 124 does not use any common-mode feedback circuit (CMFB), the output voltage thus cannot be controlled at a desirable level, and the circuit 30 generates common-mode gain of two (2) with respect to the input common-mode voltage disturbance (ΔVcm), where the common-mode gain is equal to the differential mode gain. When the circuit 30 is applied, for example, to the cascaded stages of a pipelined analog-to-digital converter, as shown in FIG. 4, the common-mode gain of two (2) in each stage will probably make the later stage(s) saturated, causing the converter to malfunction. The pipelined analog-to-digital converter mentioned above is discussed in another patent application entitled “Stage-Resolution Scalable Opamp-Sharing Technique for Pipelined/Cyclic ADC” owned by the same assignee of the present application, the disclosure of which is hereby incorporated by reference.
The pseudo-differential switched-capacitor circuit as discussed above needs an effective mechanism to stabilize the common-mode voltage in order to keep sufficient signal swing for a low operating-voltage process. There are some techniques disclosed in the scientific/technical literature, which are discussed in the following paragraphs.
1. Common-Mode Feedback Circuit (CMFB)
The common-mode feedback circuit (CMFB) is the most direct answer to stabilizing the output common-mode voltage. FIG. 5 shows a pseudo-differential switched-capacitor circuit 50 (which is the equivalent of the amplify-phase circuit 30 in FIG. 3) using the CMFB 102, which keeps the output common-mode level at a desirable common-mode voltage (Vcm). Owing to the lack of tail current transistor, the common-mode voltage disturbance (ΔVcm) at the input node will disadvantageously result in current change in the circuit 50, thereby degrading the circuit performance in accordance with the input common-mode voltage disturbance (ΔVcm).
2. Differential Floating Sampling Scheme (DFS)
For the pseudo-differential switched-capacitor circuit, in the sample phase, the common-mode voltage disturbance (ΔVcm) is sampled by two capacitors, or equivalently speaking, common-mode voltage disturbance ΔVcm, provided that the two capacitors have the same capacitance C, is sampled by the two capacitors, resulting in common-mode gain of two (2). It may be possible to decrease the common-mode gain to relieve the effect of the common-mode voltage disturbance on the circuit, by decreasing the degree of sampling the common-mode voltage disturbance (ΔVcm). This goal can be obtained, for example, by applying a differential floating sampling scheme (DFS) as shown in FIG. 6, which is disclosed, for example, J. Li and U. K. Moon, “A 1.8-V 67-mW 10-bit 100 MS/s pipelined ADC using time-shifted CDS technique,” IEEE J. Solid-State Circuits, vol. 39, pp. 1468-1476, September 2004, the disclosure of which is hereby incorporated by reference. The circuit 60 in FIG. 6 uses two single-ended amplifiers in the positive and negative path respectively, and has a pseudo-differential architecture similar to that in FIG. 3. In the sample phase (with active ψ1), the upper plates (connected to the input nodes of the amplifiers 602A/602B) of the capacitor C1 and the capacitor C4 receive common-mode voltage (via ψ1-controlled switches), while the upper plates of the capacitor C2 and the capacitor C3 are floating (due to floating switch surrounded by the dash rectangular). The capacitor C1 or the capacitor C4 will sample the common-mode voltage disturbance (ΔVcm) to get the common-mode voltage disturbance charge (1xCx ΔVcm), but the floating capacitor C2 or the capacitor C3 will bypass the input common-mode disturbance. Accordingly, the common-mode gain of the circuit 60 has a value of one (1), and the input common-mode voltage disturbance will not be amplified. The circuit 60 according to the differential floating sampling scheme (DFS) needs no additional active circuit, such as the CMFB, and may substantially improve its power consumption. However, the switches of the circuit 60 disadvantageously give rise to charge injection effect, which makes additional common-mode voltage drift. When the circuit 60 is applied, for example, to the cascaded stages of a pipelined analog-to-digital converter, as shown in FIG. 4, the later stage(s) probably possesses large common-mode voltage drift, therefore decreasing the circuit performance.
3. Common-Mode Feed-forward Scheme (CMFF)
FIG. 7A shows a circuit 70 according to common-mode feed-forward scheme (CMFF), which has a stabilization concept similar to that in FIG. 6, but can further reduce the common-mode gain toward zero (0). FIG. 7A to FIG. 7C are disclosed, for example,
T. Ueno, T. Ito, et al., “A 1.2 V, 24 mW/ch, 10 bit, 80 M Sample/s pipelined A/D converters,” Proc. Of CICC, pp. 501-504, September 2006, the disclosure of which is hereby incorporated by reference. The circuit utilizes a common-mode (CM) detector 702 to detect input common-mode voltage, and then utilizes an analog adder/subtractor 704 to make the common-mode voltage disturbance to be reflected onto the upper plate of the capacitor. As a result, no common-mode voltage disturbance (ΔVcm) will be sampled, and the circuit 70 thus has no common-mode gain, thereby effectively eliminating the common-mode voltage drift. However, the circuit 70 still has the common-mode voltage drift due to the charge injection effect caused by associated switches.
FIG. 7B shows a detailed circuit of the common-mode (CM) detector 702 in FIG. 7A, and FIG. 7C shows a detailed circuit of the analog adder/subtractor 704 in FIG. 7A. The analog adder/subtractor 704 is two-stage amplifier, which the first stage has a four-input single-ended amplifier 7041, and the second stage 7042 is a common source amplifier. The analog adder/subtractor 704 uses Miller compensation technique to accomplish its frequency compensation. The output of the circuit 704 is connected to the input as an amplifier with gain of one (1). As the CMFF circuit 70 does not utilize feedback control to decrease the common-mode voltage, the finite gain error and the settling error of the analog adder/subtractor 704 will still be amplified by the circuit 70. In order to decrease the common-mode voltage disturbance, the open-circuit gain and the bandwidth of the analog adder/subtractor 704 should both be increased, which advantageously consume more power.
Due to the disadvantages of the prior techniques for the common mode stabilization of the peudo-differential switched-capacitor circuits, a need has arisen to propose an innovative technique that could effectively decrease the common-mode voltage drift due to the charge injection effect caused by associated switches.